Modern digital systems and communications devices often include components to generate periodic waveforms or signals having tuned frequency and/or phase characteristics. For example, frequency synthesizers are often employed in communications systems for generating programmable frequencies, which are used for timing or frequency translation purposes. Phase locked loop (PLL) systems are closed loop circuits often employed in frequency synthesis applications, in which an oscillator is controlled such that the oscillator maintains a constant phase angle relative to a reference signal. A conventional PLL system 10 is illustrated in FIG. 1, including a forward path with a phase detector 14 (e.g., sometimes referred to as a phase-frequency detector) receiving a frequency reference input 12, a charge pump 16, a loop filter 18, and a voltage controlled oscillator (VCO) 20 that generates a frequency output signal 22. The VCO 20 is a circuit that generates an output 22 having a frequency that is proportional to the VCO input voltage, sometimes referred to as the VCO tuning voltage.
A feedback circuit is provided, including a divide by N counter 24 that divides the output signal by an integer number “N” to generate a feedback signal that is compared to the frequency reference input 12 by the phase detector 14. The feedback signal is generally at a lower frequency than the frequency output signal 22, whereby a relatively low frequency reference input 12 (e.g., a crystal oscillator circuit) can be used to create a higher frequency output 22. The phase detector 14 compares the feedback frequency signal with the reference input signal 12 and generates an output that represents the phase difference of the two input signals. The phase detector output is typically and analog circuit that generates a single DC voltage, or a digital circuit implementing an exclusive-OR (XOR) or similar function by which one or more digital signals are generated, to control the charge pump 16. In the system 10, the phase detector output signal includes an UP signal and a DOWN signal that drive sourcing and sinking current sources of the charge pump 16, so as to increase or decrease the VCO tuning voltage input, respectively.
If the frequency reference input 12 and the feedback signal differ in frequency, the detector output (e.g., one of the UP and DOWN detector output signals) is a periodic signal at the difference frequency, sometimes referred to as a phase-error signal. This signal is used to generate the charge pump output, which is then filtered in the loop filter 18, where the loop filter 18 typically implements a low-pass transfer function. The output of the filter 18 is provided as the VCO tuning voltage input, used to set the VCO output frequency (e.g., the frequency output 22). For a given frequency reference input 12, the PLL system 10 eventually “locks” into a stable closed loop steady-state condition, in which the VCO 20 maintains a generally fixed relationship between the frequency output 22 and the frequency reference input 12 (e.g., where the output frequency is N times the input frequency).
In the design of frequency synthesizers and other systems that employ PLLs, it is often desirable for the PLL to operate over a relatively wide frequency band or tuning range. At the same time, the design of closed-loop PLL systems must also account for phase noise, overshoot, settling time, and spurious response, wherein the VCO tuning sensitivity affects the closed loop performance and stability. Conventional PLL systems, such as the system 10 of FIG. 1 typically include VCOs 20 having non-linear tuning sensitivity, measured in KHz/V or MHz/V. The tuning sensitivity variation of the VCO 20, in turn, limits the PLL system performance, wherein maximizing the system tuning range typically leads to highly non-linear VCO control characteristics over the full possible voltage range of the charge pump 16. Accordingly, there is a need for improved PLL systems by which the shortcomings of VCO tuning sensitivity variations can be mitigated.